1. Field of the Invention
The present invention relates to a method of manufacturing a semiconductor device and more particularly, to a method of manufacturing an MOSFET allowing compensation for degradation of its lifetime caused by hot carriers.
2. Description of the Background Art
In the field of LSI, there has been a growing trend towards microstructure and high degree of integration of an element, thereby allowing reduction in manufacturing cost and increase in operating speed. On the other hand, microstructure of the element will induce high electric field within a semiconductor substrate, causing degradation of characteristic of the element resulting from hot carriers. More particularly, carriers are accelerated by high electric field near drain to have high energy, pass over an energy barrier between the semiconductor substrate and a gate insulating film and get into the gate insulating film. As a result, there arises fluctuation in threshold voltage Vth of an MOSFET. In the present specification and claims, degradation of the element characteristic thereby caused is called as “lifetime degradation caused by Vth shift”. The lifetime degradation caused by Vth shift can be compensated for by relaxing high electric field near the drain. For relaxation of high electric field near the drain, an LDD (lightly doped drain) structure has been widely adopted.
FIGS. 15 through 18 are sectional views illustrating a method of manufacturing a semiconductor device having an LDD structure in the background art following the sequence of its steps. First, with reference to FIG. 15, a p-type silicon substrate 101 is prepared. A silicon oxide film is thereafter provided on the entire upper surface of the silicon substrate 101 by thermal oxidation. Next, a polysilicon film is provided on the entire surface of the silicon oxide film by CVD. The silicon oxide film and the polysilicon film are then patterned using photolithography and anisotropic dry etching, thereby forming a gate structure 104 including a gate insulating film 102 and a gate electrode 103.
With reference to FIG. 16, the subsequent step is ion implantation implanting phosphorous ions 105 into the upper surface of the silicon substrate 101 under the conditions of 25 keV and 5E13 cm−2. At this time, the gate structure 104 serves as a mask against ion implantation. Thereafter annealing is performed for about 30 seconds at a temperature of 900° C., inducing thermal diffusion of the implanted phosphorous ions 105 in the silicon substrate 101. LDD regions 106 forming a pair are thereby provided in the upper surface of the silicon substrate 101.
Next, with reference to FIG. 17, using CVD, a silicon nitride film is entirely provided on the structure gained in FIG. 16. This silicon nitride film is thereafter etched by anisotropic dry etching, thereby forming sidewalls 107 on the side surfaces of the gate structure 104.
With reference to FIG. 18, the subsequent step is ion implantation implanting arsenic ions 108 into the upper surface of the silicon substrate 101 under the conditions of 60 keV and 5E15 cm−2. At this time, the gate structure 104 and the sidewalls 107 each serve as a mask against ion implantation. Thereafter annealing is performed for about 30 seconds at a temperature of 1000° C., inducing thermal diffusion of the implanted arsenic ions 108 in the silicon substrate 101. Source/drain regions 109 forming a pair are thereby provided in the upper surface of the silicon substrate 101.
According to the semiconductor device manufactured by the background-art method, the LDD regions 106 of relatively low concentration extend under the sidewalls 107 as illustrated in FIG. 18. Due to this, depletion layer of the source/drain regions 109 extends as far as the regions defined under the sidewalls 107. As a result, the high electric field near the drain can be relaxed, thereby allowing compensation for degradation of lifetime caused by Vth shift.
As described above, the existence of the LDD regions 106 results in compensation for lifetime degradation caused by Vth shift. On the other hand, hot carriers getting into the lower parts of the sidewalls 107 from the LDD regions 106 may be another cause of degradation of element characteristic. More particularly, by repulsive force of carriers accumulated in the lower part of each sidewall 107 (corresponding to electrons when the device is an NMOSFET), carriers (electrons) near the upper surface of each LDD region 106 are pressed in a depth direction of the silicon substrate 101. The concentration of carriers in the vicinity of the upper surface of the LDD region 106 is thereby lowered, resulting in increase in parasitic resistance and reduction in drain current. In the present specification and claims, the degradation of the element characteristic thereby caused is called as “lifetime degradation caused by current reduction”.
FIG. 19 is a graph showing relation between a width W of the sidewall 107 (see FIG. 17) and hot carrier lifetime. The hot carrier lifetime includes device lifetime defined by Vth shift and lifetime defined by current reduction. It is seen from FIG. 19 that as the sidewall 107 decreases in width W, lifetime K1 defined by current reduction increases. This is because the number of hot carriers getting into the lower part of the sidewall 107 is reduced as the sidewall 107 decreases in width W. On the other hand, it is also seen that as the sidewall 107 increases in width W, lifetime K2 defined by Vth shift increases. This is because degree of relaxation of maximum electric field in the boundary between a channel region under the gate structure 104 and the LDD region 106 increases as the sidewall 107 increases in width W. There is a trade-off between the lifetimes K1 and K2 accordingly, providing a proper range for the sidewall width W within which both the lifetimes K1 and K2 each have a reference value k or more. Namely, according to the illustrative example in FIG. 19, when the sidewall width W is set to have a value falling within a range of W1 to W2, the lifetimes K1 and K2 will each have the reference value k or more.
From a practical design standpoint of the MOSFET, however, sidewall width may be determined in consideration of element characteristics other than the lifetimes K1 and K2. More particularly, in many cases, sidewall width may be set to have a value beyond the foregoing proper range for the purpose of suppressing short channel effect. With reference to FIG. 19, when the sidewall width W is set to be W3 giving a higher priority to short channel characteristic, it is seen that the lifetime K2 exceeds the reference value k yet the lifetime K1 fails to reach the value k.
As described, according to the background-art method of manufacturing a semiconductor device, the sidewall width having a value beyond the proper range has resulted in the problem of degradation of lifetime caused by current reduction.